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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2008
- 발행연도
- 2008.7
- 수록면
- 1,093 - 1,096 (4page)
이용수
초록· 키워드
오류제보하기
This paper proposes an efficient hardware allocation algorithm for optical hardware architecture design.
The proposed algorithm works on scheduled input graph and allocates binds function-al units, registers and interconnections by considering interdependency between operations and memory in elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. Also, the register allocation is especially executes the allocation optimal using graph coloring techniques. Therefore the overall resource is reduced.
The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.
The proposed algorithm works on scheduled input graph and allocates binds function-al units, registers and interconnections by considering interdependency between operations and memory in elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. Also, the register allocation is especially executes the allocation optimal using graph coloring techniques. Therefore the overall resource is reduced.
The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.
목차
Abstract
1. Introduction
2. The proposed an efficient hardware allocation algorithm
3. The result of experiments
4. Conclusion
Reference
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